Integrated circuits commonly employ clock signals for a variety of purposes including, for example, to coordinate the timing of various actions taken by or operations performed by the integrated circuits. Not withstanding the ubiquity of clock signals in integrated circuits, there are several limitations that can occur in various integrated circuits associated with the use of such clock signals.
First, many integrated circuits employ phase-locked loops (PLLs) and it is often desired that the reference clock signals be as low as possible to reduce bill of materials (BOM) costs at the circuit board level, yet providing low reference clock signals can increase PLL jitter. Also, even though there is typically a desire to minimize power dissipation by integrated circuits, the distribution of clock signals can nevertheless entail a relatively high amount of power dissipation. Additionally, clock gating at high speeds can result in unnecessary power increases due to tight setup times of high frequency clocks. Further, conventional arrangements can suffer from excessive gain occurring at voltage controlled oscillators (VCOs), and PLL VCO bandwidth reduction is often desirable to address these issues, yet conventional clock arrangements can be inconsistent with these goals.
For at least these reasons, therefore, it would be advantageous if new or improved systems and methods for enhanced clocking operation could be achieved in integrated circuits or other electrical systems or circuits that addressed one or more of the above-discussed limitations or other limitations.